1. Field of the Invention
The present invention relates to a method of fabricating a high performance metal semiconductor field-effect transistor (MESFET), and more particularly, to a method of fabricating a MESFET having a T-shaped gate electrode with a sub-micron gate length, and source and drain electrodes which are self-aligned with the gate electrode.
2. Description of the Related Art
The benefits of sub-micron geometries in MESFETs are known in the art. Generally, device geometries below 1 micron are obtained by using techniques such as electron beam lithography and angle-evaporation, as discussed by Imai et al. in "A Sub-Half-Micron-Gate Length GaAs MESFET With New Gate Structure," IEEE Electron Device Letters, Vol. EDL-4, No. 4, p. 99 (1983). Electron beam lithography techniques, however, require expensive equipment which may not otherwise be required, and angleevaporation techniques suffer from low yield and throughput. A technique for producing sub-micron gate lengths by undercutting a multi-layered gate structure using chemical etching is disclosed in an article entitled "GaAs power Field-Effect Transistors for K-band Operation," by Taylor et al., RCA Review, Vol. 42, p. 508 (1981). While the work described by Taylor et al. does result in sub-micron gate lengths, it does not produce MESFETs having source and drain electrodes which are self-aligned with the gate electrodes ("self-aligned MESFETs"). The full potential of sub-micron geometry MESFETs cannot be exploited if the devices are not self-aligned.
To obtain self-aligned MESFETs, "T-shaped" structures have been used as shadow masks. Self-aligned techniques employing T-shaped structures are disclosed by Buiatti in U.S. Pat. No. 4,048,712, Umebachi et al. in U.S. Pat. No. 4,075,652, and Levy et al. in an article entitled "Self-Aligned Submicron Gate Digital GaAs Integrated Circuits," IEEE Electron Device Letters, Vol. EDL-4, No. 4, p. 102 (1983).
The T-shaped mask disclosed by Levy et al. is used as a shadow-mask for ion implantation. Thus, the fabrication of the T-shaped gate structure is necessarily followed by the high temperature annealing which must be performed after ion implantation. Accordingly, the gate metal must be one which will not react with the underlying substrate during the high temperature annealing, and one which has a relatively low vapor pressure so that it does not evaporate during the annealing process.
In both Buiatti and Umebachi et al. the T-shaped structures are fabricated by forming a first layer, of a material which is to be etched, over the entire surface of the semiconductor device. An etching resistant layer or layers, or a mask, is formed on a portion of the first layer. (In Buiatti the first layer becomes a gate electrode and the second layer is a mask which is ultimately removed. In Umebachi et al the various layers all become part of the gate electrode). Then etching is performed to remove the portions of the first layer which are not protected by the etching resistant layer. At the same time, the portion of the first layer which is protected by the etching resistant layer or mask is under-etched to form a T-shaped structure.
The above method of fabricating a T-shaped structure, however, does not produce a well defined gete structure. In particular, since under-etching, or lateral etching, of the first layer takes place at the same rate as the vertical etching of the first layer, the first layer which remains after etching, is much narrower at the top than at the bottom. Specifically, since lateral etching of the bottom of the first layer does not begin to occur until almost the entire thickness of the first layer has been etched, lateral etching at the bottom of the first layer does not progress very far past the edge of the etching resistant layer or mask. Thus, the chance of shorting between the gate electrode and self-aligned source and drain electrodes is always present when the gate electrode is formed in this manner. Furthermore, since lateral etching of the top of the first layer continues during almost the entire etching process, the first layer which remains after etching is much narrower at the top than at the bottom, so that it is almost triangular in crosssection.
In the case of Umebachi et al., the etching resistant layer remains after the etching is completed to become the upper, or wider, portion of the T-shaped gate electrode. As a result, the narrowness of the top of the first layer of the T-shaped structure creates increased resistivity and greatly decreases the structural stability of the gate electrode. In the case of Buiatti, where the etching resistant mask is removed, the top of the gate electrode is very narrow. Therefore, it is extremely difficult to form gate electrode contacts or to form further gate layers, and the gate electrode has an increased resistivity. Importantly, since the etching resistant layer or mask is formed by normal photolithography which cannot produce sub-micron dimensions, and since etching of the bottom of the first layer of the T-shaped structure does not progress very far past (under) the edge of the mask, it is extremely difficult to produce sub-micron gate geometries using methods such as those disclosed by Buiatti and Umebachi et al.
It is apparent, from the foregoing, that there is a need in the art for a method of fabricating MESFETs having sub-micron gate lengths and self-aligned source and drain contacts.